The present invention relates to signal conditioning systems, and more particularly to apparatus and methods for correcting duty cycle distortion.
In many electronic circuit applications, it is desirable to generate a clock signal having a duty cycle as near to 50% as possible. For example, in chip-to-chip signaling applications in which data is transmitted or received on both rising and falling edges of a clock, it is important that successive rising and falling edges of the clock signal are evenly spaced in time. Otherwise, setup and hold requirements of signaling components may be not be met during the shorter half-cycle. Applications that employ delay-locked loop (DLL) circuits are also sensitive to uneven spacing between successive rising and falling clock signal edges, particularly when they include mixing circuitry operating at the same frequency as the reference clock. In that case, uneven spacing between successive rising and falling edges of the incoming clock signal usually results in unequal spacing in the phase offsets of the mixer output signals, degrading the delay locking performance of the circuit.
FIGS. 1A, 1B and 1C illustrate a prior art duty cycle correction circuit 12 and corresponding input and output clock waveforms. The duty cycle correction circuit 12, referred to herein as a level-shifting corrector, receives an input clock signal (ICLK) and its complement (ICLK ) at respective inputs of a differential amplifier pair 14A, 14B. The differential pair 14A, 14B is biased by a current I1 drawn by a constant current source 15. The drain nodes of the differential pair, N1 and N2, are coupled to a supply voltage through respective resistive elements R1 and R2 (typically implemented by diode-configured transistors), and are coupled to ground through respective capacitive elements C1 and C2. Nodes N1 and N2 are also coupled to inputs of a buffer circuit 18 which isolates output clock signals OCLK and OCLK .
Looking at the left leg of the differential pair 14A, 14B, as ICLK goes high, the voltage at N1 begins to be pulled down through R1, discharging C1. Conversely, when ICLK goes low, the voltage at N1 is pulled up through R1, charging C1 with time constant R1C1. The net effect of this operation is to produce an output clock signal, OCLK, which is inverted and has slowed rising and falling edges relative to ICLK. The resistive and capacitive elements are balanced between the right and left legs (i.e., R2=R1 and C2=C1), so the right leg of the differential pair produces OCLK  with similar inversion and slowed rising and falling edges relative to ICLK .
A second differential amplifier pair 16A, 16B is coupled to nodes N1 and N2, and is biased by a current I2 drawn by constant current source 17. A charge pump 21 is coupled to receive the output clock signals, OCLK and OCLK , and to charge capacitive elements C3 and C4 to steady state voltages according to the respective on-times of the output clock signals. Thus, if OCLK and OCLK  are each at precisely 50% duty cycle, the voltage developed on C3 and C4 is equal, resulting in equal currents through the left and right legs of the second differential amplifier pair 16A, 16B (i.e., IS1=IS2) In this case, and currents IS1 and IS2 are said to be at level bias (I2/2), and OCLK and OCLK  each swing equally about a threshold voltage (VMID), that is midway between nominal high and low signal levels. By contrast, if the duty cycle of OCLK exceeds 50% (meaning that the duty cycle of OCLK  is correspondingly less than 50%), a higher voltage is developed on C4 than on C3 causing IS1 to exceed level bias and IS2 to fall below level bias. An increased steady state voltage drop across R1 results from the increased IS1, and causes the DC level of OCLK to shift downward by an amount equal to (IS1xe2x88x92I2/2)*R1. Conversely, a decreased steady state voltage drop across R2 results from the decreased IS2 and causes the DC level of OCLK  to shift upward by an amount equal to (I2/2xe2x88x92IS2)*R2.
FIGS. 1B and 1C illustrate the situation described above, in which the duty cycle distortion in ICLK and ICLK  result in a downward shift in the DC level of OCLK and an upward shift in the DC level of OCLK . The duty cycle distortion in ICLK and ICLK  is indicated by the uneven time periods (T1 and T2) for the half cycles that make up each complete clock cycle (TP). Because the rising and falling edges of OCLK and OCLK  have been slowed relative to the input clock signals, shifts in the levels of OCLK and OCLK  have a pronounced effect on the time at which midpoint crossings occur. In particular, the downward shift of OCLK and the upward shift of OCLK  delays the start of period T1 and advances the end of period T1 relative to the same period of the input clocks. Conversely, the start of period T2 is advanced and the end of period T2 is delayed. The net effect is to shorten the longer of the two time periods, T1, and to extend the shorter of the two time periods, T2, thus providing output clock signals having approximately 50% duty cycle.
The level shifting duty cycle corrector of FIG. 1 has a number of undesirable characteristics. One such characteristic is that the capacitive components used to reduce the edge rates of the input clock signals must usually be selected according to a specified input clock frequency. If the circuit is operated above the specified frequency, the RC circuits used to slow the output clock edge rates may prevent the output clock signals from reaching full swing. Consequently, the output clock signals may be lost altogether if the level shifting circuit shifts the DC level such that the reduced differential swing prevents the output clock signals from crossing VMID. Conversely, if the circuit is operated at a lower than specified frequency, the edge rate reduction may be insufficient to produce the required level of duty cycle correction when the DC levels of the output clocks are shifted.
One solution to the above problem is to provide additional capacitive elements that may be selectively coupled in parallel with C1 and C2. For example, C1 and C2 may be specified according to a lowest anticipated input clock frequency, and passgates or fusible logic may be used to couple additional capacitive elements as necessary to support higher input clock frequencies. For run-time configurability, register settings may be established at system start-up to couple additional capacitive elements according to a run-time determined input clock frequency. Unfortunately, these solutions generally involve additional circuitry along with factory setting or run-time support, increasing overall system cost and complexity.
Another undesirable characteristic of the level shifting duty cycle corrector of FIG. 1 is that the level shifting circuitry itself does not scale well with frequency. Generally, the amount of DC shift required to provide duty cycle correction is inversely related to the frequency of the input clock. That is, a smaller DC shift is required at a higher frequency to provide the same percentage duty cycle correction that would be produced by a larger DC shift at a lower frequency. Unfortunately, the negative feedback loop in the level shifting duty cycle corrector shifts the DC level of the output clock signals according to the duty cycle distortion in the input clock waveform and essentially independently of the frequency of the input clock signal. Thus, even though a smaller DC shift is desired at higher frequency to correct a given percentage distortion, the level shifting corrector produces roughly the same DC shift over a wide range of frequencies.
Yet another undesirable characteristic of the level shifting duty cycle corrector of FIG. 1 is that the circuit""s operation is relatively sensitive to process variations in its components. Relatively wide variances in resistive and capacitive elements are typical, as are relatively wide variances in the edge rate and drive strength of the components used to implement the current sources that draw I1 and I2. xe2x80x9cFast components,xe2x80x9d which tend to form smaller-valued resistive and capacitive elements, also tend to form stronger current sources. By contrast, xe2x80x9cslower componentsxe2x80x9d tend to form larger-valued resistive and capacitive elements, but weaker current sources. Unfortunately, this inverse relationship between the RC product and current source strength is exactly opposite that needed in the level shifting corrector of FIG. 1xe2x80x94a stronger current source is needed to discharge a larger capacitance, and a weaker current source is needed to discharge a smaller capacitance in the same time. Consequently, a relatively small variation between fast and slow components is tolerable in the level shifting corrector of FIG. 1, tending to reduce the yield of acceptable parts and correspondingly increase production costs.
Apparatus and methods for correcting duty cycle distortion in a clock signal are disclosed. In at least one embodiment, the apparatus includes circuitry to detect duty cycle distortion in an input clock signal and circuitry to asymmetrically adjust the edge rates of successive rising and falling edges of the clock signal to reduce the duty cycle distortion.
These and other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.